Japanese Laid-Open Patent Publication No. 2011-216740 describes a wiring substrate incorporating an electronic component such as a chip capacitor, which is a chip type capacitive element. The wiring substrate includes a core substrate, and the electronic component is arranged in a bore or cavity extending through the core substrate. Such wiring substrate is obtained through the following steps. First, a bore that extends through both surfaces (first surface, second surface) of the core substrate and has a larger size than the electronic component is formed in the core substrate. Next, a temporary holding tape is attached to one surface (first surface) of the core substrate so as to close the bore. Next, the electronic component is arranged in the bore, and the bore is filled with an insulating resin to form an insulating layer on a surface (second surface) of the core substrate on which the tape is not attached. The tape is then removed, and an insulating layer is formed on the surface (first surface) of the core substrate on which the tape was attached. Then, a predetermined number of insulating layers and wiring layers are stacked on each insulating layer.